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MOSFET Conduction Loss Calculator

Calculate MOSFET conduction power loss from drain current, Rds(on), and duty cycle using P = I squared * Rds(on) * duty. Free and instant.

Frequently Asked Questions

What is MOSFET conduction loss?

Conduction loss is the power a MOSFET dissipates while fully turned on, equal to the drain current squared times the on-resistance, scaled by the duty cycle.

Does this include switching loss?

No. This calculator covers conduction loss only. Switching loss, which happens during turn-on and turn-off transitions, is a separate term that depends on frequency and switching time.

Why should I use the hot Rds(on) value instead of the datasheet 25 degrees C figure?

Silicon MOSFETs have a positive temperature coefficient: on-resistance rises as the device heats up, often roughly doubling at 125 degrees C compared with the 25 degrees C room-temperature value. Since conduction loss is directly proportional to Rds(on), using the cold figure can underestimate the loss by about half. Check the Rds(on) versus temperature curve in the datasheet and use the value at your expected junction temperature for thermal design.

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Estimates for informational purposes only.

Important Disclaimer: Estimates for informational purposes only.

This calculator provides estimates for informational purposes only. Results are based on assumptions and may not reflect actual outcomes. Consult qualified professionals in relevant fields before making important decisions based on these results.

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How This Calculator Works

When a power MOSFET is fully turned on it behaves like a small resistor called Rds(on). Current flowing through that resistance dissipates power as heat. The conduction loss equals the drain current squared times Rds(on), scaled by the fraction of time the device conducts, which is the duty cycle. Because current is squared, even a modest rise in load current produces a much larger loss.

For a switch that is always on the duty cycle is one hundred percent. In a switching converter the device conducts only part of each cycle, so the duty cycle reduces the average conduction loss.

Worked Example

Suppose a MOSFET carries a drain current of I = 10 A with an on-resistance of Rds(on) = 0.02 Ω, conducting for a duty cycle of 50%. Apply P = I² × Rds(on) × duty:

P = (10 A)² × 0.02 Ω × 0.50 = 100 × 0.02 × 0.50 = 1 W.

Because current is squared, raising the current to 20 A at the same duty would give P = 400 × 0.02 × 0.50 = 4 W, four times the loss for twice the current.

How To Use It

Enter the drain current in amperes, the on-resistance Rds(on) in ohms, and the duty cycle in percent. The result is the average conduction power loss in watts, which sets the heat sink requirement.

Key Caveats

This is conduction loss only. Switching loss is a separate term.
Rds(on) rises with junction temperature, so use a hot-state value.
Use the RMS current for waveforms that are not flat.

MOSFET Loss Mechanisms in Detail

Total MOSFET power loss in a switching application has several distinct components. Conduction loss - what this calculator computes - is I² × R_DS(on) scaled by duty cycle. It dominates at low switching frequencies and high currents. Switching loss arises because the transistor does not transition between on and off states instantaneously; during the transition, both voltage and current are simultaneously present across the device, creating a power loss spike proportional to V_DS, I_D, and the switching frequency. Switching loss scales linearly with frequency and is driven primarily by the output capacitance C_oss and the total gate charge Q_g. Gate drive loss is Q_g × V_GS × f, which is typically small but can matter at very high frequencies. In hard-switched topologies (where the body diode conducts during dead time), body diode reverse recovery loss occurs as the diode snaps off and its stored charge is dissipated; this loss is proportional to Q_rr and switching frequency.

Temperature Dependence of R_DS(on)

Silicon MOSFETs have a positive temperature coefficient for R_DS(on), meaning on-resistance rises as the device heats up. A typical silicon MOSFET may have roughly twice the R_DS(on) at 125°C compared with the 25°C room-temperature value quoted in the datasheet. This creates a thermal feedback loop: higher current causes more loss, which raises temperature, which raises R_DS(on), which raises loss further. Thermal design must use the hot R_DS(on) value, not the room-temperature figure. Always check the R_DS(on) vs. temperature curve in the datasheet and apply the appropriate multiplier for the expected junction temperature.

Minimizing MOSFET Losses in Practice

Selecting the right MOSFET for the application requires understanding which loss mechanism dominates. At low switching frequency and high current (for example, a synchronous rectifier in a 100 kHz buck converter at 20 A), conduction loss dominates and the priority is the lowest available R_DS(on). At high switching frequency with moderate current (a 2 MHz converter at 5 A), switching loss dominates and the priority shifts to lowest gate charge Q_g and lowest C_oss, even if that means accepting slightly higher R_DS(on).

GaN (gallium nitride) and SiC (silicon carbide) MOSFETs have changed the design landscape significantly. GaN transistors have near-zero R_DS(on) temperature coefficient, very low gate charge, and no body diode reverse recovery, enabling efficient operation at 1 to 10 MHz. SiC MOSFETs handle higher voltages (600 V to 1700 V) with low R_DS(on), minimal temperature derating, and low switching losses, making them the dominant choice for EV motor inverters and grid-tied converters.

Gate Driver Design

The gate driver directly controls both conduction and switching losses. An under-driven gate (insufficient V_GS) increases R_DS(on) beyond the fully-on datasheet value, raising conduction loss. An over-driven or fast gate causes high dV/dt and dI/dt at the switching node, increasing EMI and reverse recovery losses in neighboring diodes. A gate resistor in series with the gate path slows the transition and reduces EMI at the cost of slightly increased switching loss - the optimum value is found by measurement or simulation. Dead time between the high-side and low-side gates in a half-bridge prevents shoot-through (both transistors conducting simultaneously), which would short the supply rail. Inadequate dead time causes catastrophic shoot-through current.

Thermal Management for MOSFETs

The thermal path from MOSFET junction to ambient air consists of three resistances in series. The junction-to-case resistance R_θJC is a property of the silicon die and package, given in the datasheet. The case-to-heatsink resistance R_θCS depends on the thermal interface material (thermal grease, pad, or direct solder) and mounting pressure. The heatsink-to-ambient resistance R_θSA depends on heatsink size, fin geometry, and whether forced airflow is used. Total power dissipation sets the temperature rise: ΔT = P_loss × (R_θJC + R_θCS + R_θSA). The target is to keep junction temperature T_j below 150°C for silicon or 175°C for SiC under worst-case conditions including maximum ambient temperature, maximum load current, and R_DS(on) at elevated temperature.

Thermal interface materials range from silicone grease (R_θCS ≈ 0.1 to 0.5 °C/W for a TO-247 package) to phase-change pads and solder. Graphite pads offer a repeatable and stable alternative to grease that does not pump out over thermal cycles. Always torque mounting hardware to the specified value; under-tightening raises R_θCS and over-tightening can crack the package.

Paralleling MOSFETs

Connecting multiple MOSFETs in parallel reduces the effective R_DS(on) and increases current-handling capability. Unlike bipolar transistors (which have a negative temperature coefficient of V_BE and tend toward thermal runaway in parallel), MOSFETs are self-balancing: the positive temperature coefficient of R_DS(on) means a hotter device carries more resistance, which reduces its current share and lets it cool. This makes paralleled MOSFETs reasonably robust without ballast resistors, though small gate resistors (1 to 10 Ω) in each gate lead help damp oscillations from parasitic inductance between the parallel devices.